The present invention relates generally to integrated circuits, and, more particularly, to a phase-locked loop.
Phase-locked loops (PLLs) are used in electronic devices such as radios, telecommunication systems, computers, and so forth. Using a reference clock signal, a PLL generates an oscillating signal, which is used to synchronize the operations of components of an integrated circuit.
Typically, a PLL includes a phase-frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a loop divider. To generate an oscillating signal, the PFD determines the phase difference between the reference clock signal and a feedback signal and generates up and down signals. The charge pump generates a charge pump output current that varies based on the up and down signals. The loop filter outputs a control voltage, based on the charge pump output current, to the VCO, which generates the oscillating signal and varies the frequency of the oscillating signal based on the value of the control voltage. The feedback signal is a frequency-divided version of the oscillating signal, which is provided by the loop divider. In PLLs that do not include a loop divider, the PFD receives the oscillating signal as the feedback signal.
Noise from various components of the PLL or electrical noise from the environment can affect the control voltage, which may cause the frequency of the oscillating signal to overshoot or undershoot. Overshoot may result in the oscillating signal frequency being greater than a maximum normal operational frequency of the loop divider, which may cause the loop divider to malfunction. Thus, the PFD may receive an incorrect feedback signal, which causes the PFD to continuously activate the up signal, leading to continuous charging of the loop filter, and hence, an increase in the control voltage. This in turn further increases the frequency of the oscillating signal and the PLL enters a deadlock condition. In an adaptive bandwidth PLL, undershoot increases the time required to achieve a phase lock between the oscillating signal and the reference clock signal (also known as ‘the PLL lock time’), since the charge pump output current is proportional to the control voltage. Further, during start-up, as the control voltage is at zero, the time required to charge the loop filter to a desired voltage is large. In PLLs that do not include a loop divider, overshoot in the oscillating signal frequency may result in the oscillating signal frequency being greater than the maximum normal operational frequency of the PFD, thereby causing the PFD to malfunction.
A known technique to overcome the aforementioned problems is to use a frequency bounding circuit, which controls the charge pump to vary the charge pump output current during overshoot and undershoot conditions based on a comparison of the control voltage with a fixed threshold voltage until normal PLL operation is restored. However, the control voltage can vary significantly with process-voltage-temperature (PVT) variations, which results in a large variation in frequency threshold values.
Another known technique is to reset the PLL when an overshoot occurs. However, this increases the time required to re-lock the oscillating signal to the reference clock signal. Further, this technique does not provide a solution for the undershoot condition and also does not reduce the start-up time of an adaptive bandwidth PLL.
It would be advantageous to have a PLL that controls the oscillating signal frequency during undershoot and overshoot conditions, and reduces the time required to re-lock the oscillating signal to the reference clock signal during the undershoot condition as well as the start-up time of the PLL.